 |
Name : Smitashree Mohapatra Designation : Asst.Professor Date of birth : 16-03-1987 Qualifications : M.Tech, JNTUH, 2013 B.Tech, B.P.U.T (ODISHA), 2009 Work Experience: -Teaching : 5Years - Industrial : Area of Specializations : VLSI System Design Emil ID : This email address is being protected from spambots. You need JavaScript enabled to view it. Subjects taught at U.G Level: EMT, NTL, VLSI etc. |
Scholastic Performance:
|
Course |
Board/ University |
Specialization (if any) |
Year of Completion |
% of Marks Obtained |
|
S.S.C |
B.S.E |
|
2002 |
72 |
|
INTER/ DIPLOMA |
C.H.S.E |
PCMB |
2004 |
76 |
|
B. Tech. |
BPUT |
ECE |
2009 |
80 |
|
M.Tech. |
JNTUH |
VLSI System Design |
2014 |
76.69 |
|
Ph.D |
|
|
|
|
|
If any other |
|
|
|
|
Teaching Experience in the college:
|
S.No |
College |
Designation |
Period |
Experience in years |
|
1 |
MVSR Engineering College |
Assistant Professor |
14th july,2014 to till date |
3.6 |
List of Journal Papers Published(from the date of joining in the college):
|
SNO |
Title of the paper |
Name of Journal |
Vol/Issue/page No/ISSN No |
Month & Year |
National / International |
|
1 |
Implementation of Carry select adder using CMOS full adders |
IJERT |
Vol-4, p.p no-5 |
May,2015 |
|
Number of Conferences/ Workshops/ Seminars attended(from the day of joining in the college):
|
Sl. no |
Topic |
Venue |
Dates |
|
1 |
2- day workshop on Analog VLSI Design |
CBIT, Hyderabad |
17th & 18thMarch,2017 |
|
2 |
2- Day FDP Program on Analog and Digital Circuit Design using Cadence |
MVSR Engg. College, ECE Dept. |
12th & 13th January ,2016 |
|
3 |
Five day Intensive Course on Probability Theory & Stochastic Processes
|
MVSR Engg. College, ECE Dept. |
4 - 8 January, 2016 |
|
4 |
Advance Digital Design Using Verilog HDL |
MVSR Engg. College, Nadergul |
28th to 31st Jan,2015 |
|
5 |
2- day workshop on Analog IC Design –Spec to Reality |
Joint chapter of IEEE CAS/ED Societies, Hyd section and Vasavi College of Engg. |
18th & 19thSept,2014 |
